1. Field of the Invention
The present invention relates generally to semiconductor fabrication methods and, more particularly, to methods for fabricating a non-volatile memory device having a silicon nitride barrier layer to reduce the fast erase effect.
2. Description of Related Art
Semiconductor devices typically include multiple individual components formed on or within a substrate. One such component is a memory device, which is used to store electronic data such as computer programs executed by an electronic processor and logical data operated on by the processor. Memory devices that do not require ambient power to store electronic data are commonly referred to as non-volatile memory devices. Flash memory is a specific form of non-volatile memory by which bits of logical data are stored in units of memory known as memory cells. A grouping of memory cells can be termed a word, a grouping of words can be termed a page, and a grouping of pages can be termed a sector. Data can be accessed for reading and programming by word or page, while an entire sector is commonly accessed for erasing.
A conventional flash memory cell includes a transistor characterized by a programmable threshold voltage VT. The transistor's threshold voltage can be set, or programmed, to a desired value along an analog scale between the maximum and minimum threshold voltage limits that are determined based on the design parameters for the transistor. The transistor typically comprises a stacked gate structure on a semiconductor substrate. The stacked gate structure includes a relatively thin tunnel oxide (i.e., silicon dioxide) that overlies the substrate. It also includes a doped polysilicon floating gate that overlies the tunnel oxide and an interpoly dielectric that overlies the floating gate. Lastly, a doped polysilicon control gate overlies the interpoly dielectric. The transistor also comprises source and drain regions that are self-aligned to the sidewalls of the stacked gate structure.
In general, a flash memory cell can be programmed by inducing electron injection from the drain region to the floating gate. Electrons pass through the tunnel oxide to the floating gate by a mechanism known as Fowler-Nordheim tunneling. After sufficient negative charge accumulates on the floating gate, the negative potential of the floating gate raises the threshold voltage of the associated field effect transistor (FET) and inhibits current flow through the channel region during a subsequent “read” mode. The act of discharging the floating gate, i.e., the erase function, can be carried out by inducing the electrons stored in the floating gate to move to the source region. There are numerous ways to move electrons to or from the floating gate. For example, the electrons can be electrically drawn or, alternatively, they can be drawn using ultraviolet radiation.
It is desirable for flash memory cells to exhibit consistent erase times. However, when prior art fabrication methods are used, a fast erase effect can occur in which some memory cells erase at a faster rate than others. The fast erase effect is pronounced in the earlier program and erase cycles. In particular, the threshold voltage of the faster-erasing memory cells may be undesirably lower than the threshold voltage of other memory cells. The faster-erasing memory cells thus may overerase, causing current leakage. Excessive leakage currents can have adverse effects on the operation of the flash memory cell. For example, the leakage currents of multiple cells in a column have a summing effect of leakage current on the bit-line and may result in an incorrect data reading. A need thus exists in the prior art to reduce the fast erase effect on memory cells. A further need exists to reduce threshold voltage differences among multiple memory cells between the initial erase and the erase after many cycles.